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FAN6520A
Single Synchronous Buck PWM Controller
Features
* Output Range 0.8V to VIN - 0.8V Internal Reference - 1.5% Over Line Voltage and Temperature * Drives N-Channel MOSFETs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle * Lossless, Programmable Over-current Protection - Uses Upper MOSFET's RDS(ON) * Small Converter Size - 300kHz Fixed Frequency Oscillator - Internal Soft-Start - 8-Lead SOIC
General Description
The FAN6520A makes simple work out of implementing a complete control and protection scheme for a DC-DC stepdown converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, the FAN6520A integrates the control, output adjustment, monitoring and protection functions into a single 8-lead package. The FAN6520A is easy to use, employs a single feedback loop, and voltage-mode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost. The error amplifier features a 15MHz gainbandwidth product and an 8V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. The IC monitors the drop across the upper MOSFET and inhibits PWM operation appropriately to protect against over-current conditions. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor. The FAN6520A is rated for operation from 0 to +70C with the FAN6520AI rated from -40 to +85C.
Applications
* * * * * Power Supplies for PC Subsystems and Peripherals MCH, GTL, and AGP Supplies Cable Modems, Set Top Boxes, and DSL Modems DSP, Memory Low-Voltage Distributed Power Supplies
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FAN6520A
PRODUCT SPECIFICATION
Pin Configuration
BOOT HDRV GND LDRV
1 2 3 4 FAN6520A
8 7 6 5
SW COMP/OCSET/SD FB VCC
FAN6520AM 8-pin SOIC Package
Pin Definitions
Pin # 1 2 Pin Name BOOT HDRV Pin Function Description Bootstrap Supply Input. Provides a boosted voltage to the high-side MOSFET driver. Connect to bootstrap capacitor as shown in Figure 1. High Side Gate Drive Output. Connect to the gate of the high-side power MOSFET(s). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off. Ground. The signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available. Connect directly to source of low-side MOSFET(s). Low Side Gate Drive Output. Connect to the gate of the low-side power MOSFET(s). This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. VCC. Provides bias power to the IC and the drive voltage for LDRV. Bypass with a ceramic capacitor as close to this pin as possible. Feedback. This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter.
3
GND
4
LDRV
5 6
VCC FB
7
COMP/ COMP/OCSET/SD. This is a multiplexed pin. During operation, the output of the error OCSET/SD amplifier drives this pin. During a short period of time following power-on reset (POR), this pin is used to determine the over-current threshold of the converter. Pulling COMP/OCSET to a level below 0.8V disables the controller. Disabling the controller causes the oscillator to stop, the HDRV and LDRV outputs to be held low, and the soft-start circuitry to re-arm. SW Switch Node Input. Connect as shown in Figure 1. The SW pin provides return for the high-side bootstrapped driver, is a sense point for the adaptive shoot-thru protection, and is used for monitoring the drop across Q1's RDS(ON) for current limit.
8
2
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FAN6520A
PRODUCT SPECIFICATION
Typical Application
+5V D BOOT 1 VCC C VCC BOOT C BOOT C BULK Q1 2 HDRV SW Q2 LDRV GND FB RS R OFFSET LOUT +VOUT C OUT C HF
5
R OCSET
FAN6520A
8
4 3 COMP/OCSET 7 6
RF
CF CI
Figure 1. Typical Application
VCC POR / SOFT START SAMPLE & HOLD COMP/OCSET FB
- + 0.8V ERROR AMP 20A - + OC - + PWM PWM
BOOT
INHIBIT
HDRV SW
GATE CONTROL LOGIC
VCC
LDRV GND
OSC
Figure 2. Functional Block Diagram
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FAN6520A
PRODUCT SPECIFICATION
Absolute Maximum Ratings
Absolute maximum ratings are the values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Parameter VCC to GND VBOOT to GND HDRV (VBOOT - VSW) LDRV SW to PGND All other pins Continuous Transient ( t < 50nsec, F < 500kHz) -0.5 -0.5 -3 Min. Max. 6 15 6 6 6 7 5.5 Units V V V V V V V
Thermal Information
Parameter Storage Temperature Lead Soldering Temperature, 10 seconds Vapor Phase, 60 seconds Infrared, 15 seconds Power Dissipation (PD), TA = 25C Thermal Resistance - Junction to Case JC Thermal Resistance - Junction to Ambient JA 40 140 Min. -65 Typ. Max. 150 300 215 220 715 Units C C C C mW C/W C/W
Recommended Operating Conditions
Parameter Supply Voltage VCC Ambient Temperature (TA) Conditions VCC to PGND FAN6520A FAN6520AI Junction Temperature (TJ) Min. 4.5 0 -40 -40 Typ. 5 Max. 5.5 70 85 125 Units V C C C
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PRODUCT SPECIFICATION
FAN6520A
Electrical Specifications
Parameter Supply Current VCC Current Power-On Reset Rising VCC POR Threshold VCC POR Threshold Hysteresis Oscillator Frequency Ramp Amplitude Reference Reference Voltage Error Amplifier DC Gain Gain - Bandwidth Product Slew Rate Gate Drivers HDRV pull-up resistance HDRV pull-down resistance LDRV pull-up resistance LDRV pull-down resistance Protection/Disable OCSET Current Source Disable Threshold
VCC = 5V, and TA = 25C using circuit in Figure 1 unless otherwise noted. The * denotes specifications which apply over the full operating temperature range. Symbol IVCC POR Conditions HDRV, LDRV open * * Min. 1.5 4.00 Typ. 2.4 4.22 170 FOSC VOSC VREF TA = 0 to 70C FAN6520AI FAN6520A FAN6520AI * * * * * 788 780 250 230 300 300 1.5 800 800 88 GBWP S/R RHUP RHDN RLUP RLDN IOCSET VDISABLE FAN6520A FAN6520AI * * 17 14 15 8 2.5 2.0 2.5 1.0 20 20 800 22 24 812 820 340 340 Max. 3.8 4.45 Units mA V mV kHz kHz Vp-p mV mV dB MHz V/s A A mV
Notes: 1. All limits at operating temperature extremes are guaranteed by design, characterization and statistical quality control. 2. AC specifications guaranteed by design/characterization (not production tested).
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FAN6520A
PRODUCT SPECIFICATION
Circuit Description
Initialization
The FAN6520A automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. When the supply voltage exceeds its POR threshold, the IC initiates the Over-current Protection (OCP) sample and hold operation. Upon completion of the OCP sampling and hold operation, the POR function initiates the soft-start operation.
The over-current function will trip at a peak inductor current (IPEAK) determined by:
I OCSET x R OCSET I PEAK = ----------------------------------------------R DS ( ON ) (1)
Over-Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, RDS(ON), to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating the need for a current-sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the overcurrent trip level (see Typical Application diagram). Immediately following POR, the FAN6520A initiates the Over-current Protection sampling and hold operation. First, the internal error amplifier is disabled. This allows an internal 20A current sink to develop a voltage across ROCSET. The FAN6520A then samples this voltage at the COMP pin. This sampled voltage, which is referenced to the VCC pin, is held internally as the Over-current Set Point. When the voltage across the upper MOSFET, which is also referenced to the VCC pin, exceeds the Over-current Set Point, the over-current function initiates a soft-start sequence. Figure 3 shows the inductor current after a fault is introduced while running at 15A. The continuous fault causes the FAN6520A to go into a hiccup mode with a typical period of 25ms. The inductor current increases to 18A during the soft-start interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions shown in Figure 3 is only 1.5W.
where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET's RDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the ROCSET resistor from the equation above with: 1. 2. 3. The maximum RDS(ON) at the highest junction temperature. Determine IPEAK for I PEAK > I OUT ( MAX ) + I , ---where I is the output inductor ripple current. For an equation for the ripple current see "Output Inductor (Lout)" under Component Selection. Internal circuitry of the FAN6520A will not recognize a voltage drop across ROCSET larger than 0.5V. Any voltage drop across ROCSET that is greater than 0.5V will set the overcurrent trip point to:
0.5V I PEAK = ---------------------R DS ( ON ) 2
The minimum IOCSET from the specification table.
An overcurrent trip cycles the soft-start function.
Soft-Start
The POR function initiates the soft-start sequence after the over-current set point has been sampled. Soft-start clamps the error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated soft-start voltage. Figure 4 shows a typical start up interval where the COMP/OCSET pin has been released from a grounded (system shutdown) state. Initially, the COMP/OCSET is used to sample the over-current setpoint by disabling the error amplifier and drawing 20A through ROCSET. Once the over-current level has been sampled, the soft-start function is initiated. The clamp on the error amplifier (COMP/OCSET pin) initially controls the converter's output voltage during soft-start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates SW pulses of increasing width that charge the output capacitor(s). When the internally generated soft-start voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically takes about 11ms.
OUTPUT INDUCTOR CURRENT 5A/DIV.
Figure 3. Over-Current Operation
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PRODUCT SPECIFICATION
FAN6520A
Vin Q1 HDRV SW Q2 LDRV L OUT CIN +VOUT COUT
Figure 5. Printed Circuit Board Power and Ground Planes or Islands Figure 4. Soft-Start Interval
The FAN6520A incorporates a MOSFET shoot-through protection method which allows a converter to both sink and source current. Care should be exercised when designing a converter with the FAN6520A when it is known that the converter may sink current. When the converter is sinking current, it is behaving as a boost converter that is regulating its input voltage. This means that the converter is boosting current into the VCC rail, which supplies the bias voltage to the FAN6520A. If this current has nowhere to go--such as to other distributed loads on the VCC rail, through a voltage limiting protection device, or other methods--the capacitance on the VCC bus will absorb the current. This situation will allow the voltage level of the VCC rail to increase. If the voltage level of the rail is boosted to a level that exceeds the maximum voltage rating of the FAN6520A, then the IC will experience an irreversible failure and the converter will no longer be operational. Ensure that there is a path for the current to follow other than the capacitance on the rail to prevent this failure mode.
Figure 5 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 5 should be located as close together as possible. Please note that the capacitors CIN and COUT may each represent numerous physical capacitors. Locate the FAN6520A within two inches of the Q1 and Q2 MOSFETs. The circuit traces for the MOSFETs' gate and source connections from the FAN6520A must be sized to handle up to 1A peak current. Figure 5 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET close to the COMP/OCSET pin because the internal current source is only 20A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC as practical.
Vin Q1 CBOOT L OUT COUT Q2 VCC COMP/OCSET GND +5V CVCC
LOAD
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. Use wide, short-printed circuit traces to minimize these interconnecting impedances. The critical components should be located as close together as possible, using ground plane construction or single point grounding.
+5V DBOOT BOOT
FAN 6520A
ROCSET
SW
Figure 6. PC Board Small Signal Layout Guidelines
LOAD
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FAN6520A
PRODUCT SPECIFICATION
Feedback Compensation
Figure 7 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the SW node. The PWM wave is smoothed by the output LC filter (LOUT and COUT).
VIN OSC L OUT
SW PWM
1.
The compensation network consists of the error amplifier (internal to the FAN6520A) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (F0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at F0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7.
1 F Z1 = --------------------2R 2 C 1 (17) (18)
+VOUT
COUT
ESR
1 F P1 = ---------------------------------------C1 C2 ------------------- 2R 2 - C1 + C2 1 F Z2 = --------------------------------------2C 3 ( R 1 + R 3 ) 1 F P2 = --------------------2R 3 C 3
Q2 +5V ZFB
(19) (20)
FB
COMP
ERROR AMP 0.8V
ZIN
Use the following steps to locate the poles and zeros of the compensation network: 2. Pick gain (R2/R1) for the desired converter bandwidth. Place 1st zero below the filter's double pole (~75% FLC). Place 2nd zero at filter's double pole. Place 1st pole at the ESR zero. Place 2nd pole at half the switching frequency. Check gain against the error amplifier's open-loop gain. Estimate phase margin. Repeat if necessary.
DETAILED COMPENSATION COMPONENTS
3. 4. 5.
VOUT
ZFB
C1 R2
C2 C3
ZIN
R3 R1
6. 7. 8.
COMP
ERROR AMP
FB
0.8V
Figure 7. Voltage Mode Buck Converter Compensation Design
The modulator transfer function is the small-signal transfer function of VOUT/VCOMP. This function is dominated by a DC Gain and the output filter (LOUT and COUT), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage VOSC. The following equations define the modulator break frequencies as a function of the output LC filter:
1 F LC = -----------------------2 L x C 1 F ESR = -----------------------------------2 x ESR x C (15)
Figure 8 shows an asymptotic plot of the DC-DC converter's gain vs. frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 8. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 8 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function by the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with a -20dB/decade slope and a phase margin greater than 45. Include worst case component variations when determining phase margin.
(16)
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PRODUCT SPECIFICATION
FAN6520A
Output Inductor (LOUT)
100 80 60 GAIN (dB) 40 20 0 -20 -40 FLC -60 10 100 1K 10K FESR 100K 1M 10M 20LOG (R2/R1) MODULATOR GAIN 20LOG (VIN/DVOSC) COMPENSATION GAIN CLOSED LOOP GAIN OPEN LOOP ERROR AMP GAIN FZ1 FZ2 FP1 FP2
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage (V) and current (I) are approximated by the following equations:
V IN - V OUT I = ----------------------------F SW x L V ESR x I (1)
FREQUENCY (Hz)
Figure 8. Asymptotic Bode Plot of Converter Gain
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout.
Component Selection
Output Capacitors (COUT)
Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. Effective Series Resistance (ESR) and voltage rating are typically the prime considerations for the bulk filter capacitors, rather than actual capacitance requirements. High-frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the performance of these low inductance components. Consult with the load manufacturer on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switchingregulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
Increasing the inductance value reduces the ripple current and voltage. However, a large inductance value reduces the converter's ability to quickly respond to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the FAN6520A will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. Depending upon the whether there is a load application or a load removal, the response time to a load transient (ISTEP) is different. The following equations give the approximate response time interval for application and removal of a transient load:
L x I STEP T RISE = ----------------------------V IN - V OUT L x I STEP T FALL = -----------------------V OUT
where TRISE is the response time to the application of a positive ISTEP, and TFALL is the response time to a load removal (negative ISTEP). The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time.
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high-frequency decoupling and bulk capacitors to supply the current needed each time Q1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2. The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and the largest
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FAN6520A
PRODUCT SPECIFICATION
RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement (IRMS) for the input capacitor of a buck regulator is:
I RMS = I L ( D - D )
OUT where the converter duty cycle; D = -------------- . For a 2
Where PH(R) and PH(F) are internal dissipations for the rising and falling edges respectively:
R HUP P H ( R ) = P Q1 x ------------------------------------------R HUP + R E + R G R HDN P H ( F ) = P Q1 x ------------------------------------------R HDN + R E + R G (7)
(8)
(2) V
where:
PQ1 = QG1 x VGS(Q1) x FSW (9)
V IN
through-hole design, several electrolytic capacitors may be needed. For surface-mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor's surge current rating. The capacitors must be capable of handling the surge current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
Where QG1 is total gate charge of Q1 for its applied VGS. As described in the equations above, the total power consumed in driving the gate is divided in proportion to the resistances in series with the MOSFET's internal gate node as shown in Figure 9.
BOOT Q1 RHUP
HDRV RE
G
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor (CBOOT) and the internal diode, as shown in Figure 1. Selection of these components should be done after the high-side MOSFET has been chosen. The required capacitance is determined using the following equation:
QG C BOOT = --------------------V BOOT (3)
RG
RHDN
SW
S
Figure 9. Driver Dissipation Model
where QG is the total gate charge of the high-side MOSFET, and VBOOT is the voltage droop allowed on the high-side MOSFET drive. To prevent loss of gate drive, the bootstrap capacitance should be at least 50 times greater than the CISS of Q1.
Thermal Considerations
Total device dissipation:
PD = PQ + PHDRV + PLDRV (4)
RG is the polysilicon gate resistance, internal to the FET. RE is the external gate drive resistor implemented in many designs. Note that the introduction of RE can reduce driver power dissipation, but excess RE may cause errors in the "adaptive gate drive" circuitry. For more information please refer to Fairchild app note AN-6003, "Shoot-through" in Synchronous Buck Converters. (http://www.fairchildsemi.com/an/AN/AN-6003.pdf) PLDRV is dissipation of the lower FET driver.
PLDRV = PL(R) x PL(F) (10)
where PQ represents quiescent power dissipation:
PQ = VCC x [4mA + 0.036 (FSW - 100)] (5)
Where PH(R) and PH(F) are internal dissipations for the rising and falling edges, respectively:
R LUP P L ( R ) = P Q2 x -----------------------------------------R LUP + R E + R G R LDN P L ( F ) = P Q2 x ------------------------------------------R HDN + R E + R G (11)
where FSW is switching frequency (in kHz). PHDRV represents internal power dissipation of the upper FET driver.
PHDRV = PH(R) x PH(F) (6)
(12)
where:
PQ2 = QG2 x VGS(Q2) x FSW (13)
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PRODUCT SPECIFICATION
FAN6520A
Power MOSFET Selection
For more information on MOSFET selection for synchronous buck regulators, refer to: AN-6005: Synchronous Buck MOSFET Loss Calculations. This Fairchild app note is located at: http://www.fairchildsemi.com/an/AN/AN-6005.pdf
The driver's impedance and CISS determine t2 while t3's period is controlled by the driver's impedance and QGD. Since most of tS occurs when VGS = VSP we can use a constant current assumption for the driver to simplify the calculation of tS:
C ISS VDS C GD C ISS
Losses in a MOSFET are the sum of its switching (PSW) and conduction (PCOND) losses. In typical applications, the FAN6520A converter's output voltage is low with respect to its input voltage, therefore the lower MOSFET (Q2) is conducting the full load current for most of the cycle. Therefore choose a MOSFET for Q2 which has low RDS(ON) to minimize conduction losses. In contrast, the high-side MOSFET (Q1) has a much shorter duty cycle, and its conduction loss will therefore have less of an impact. Q1, however, sees most of the switching losses, so Q1's primary selection criteria should be gate charge.
ID
QGS QGD
4.5V
V SP V TH
High-Side Losses
Figure 10 shows a MOSFET's switching interval, with the upper graph being the voltage and current on the Drain to Source and the lower graph detailing VGS vs. time with a constant current charging the gate. The x-axis, therefore, is also representative of gate charge (QG) . CISS = CGD + CGS, and it controls t1, t2, and t4 timing. CGD receives the current from the gate driver during t3 (as VDS is falling). The gate charge (QG) parameters on the lower graph are either specified or can be derived from the MOSFET's datasheet. Assuming switching losses are about the same for both the rising edge and falling edge, Q1's switching losses, occur during the shaded time when the MOSFET has voltage across it and current through it. These losses are given by:
PUPPER = PSW + PCOND V DS x I L P SW = --------------------- x 2 x t s F SW 2 V OUT 2 P COND = -------------- x I OUT x R DS ( ON ) V IN (14) (15)
VGS
t1 t2
QG(SW)
t3 t4 t5
Figure 10. Switching Losses and QG
5V CGD RD HDRV RGATE G CGS SW
VIN
Figure 11. Drive Equivalent Circuit
Q G ( SW ) Q G ( SW ) t s -------------------- ----------------------------------------------------I DRIVER VCC - V SP ----------------------------------------------- R DRIVER + R GATE
(16)
where: PUPPER is the upper MOSFET's total losses, and PSW and PCOND are the switching and conduction losses for a given MOSFET. RDS(ON) is at the maximum junction temperature (TJ). tS is the switching period (rise or fall time) and is t2+t3 (Figure 10).
Most MOSFET vendors specify QGD and QGS. QG(SW) can be determined as: QG(SW) = QGD + QGS - QTH where QTH is the gate charge required to get the MOSFET to its threshold (VTH). For the high-side MOSFET, VDS = VIN, which can be as high as 20V in a typical portable application. Care should also be taken to include the delivery of the MOSFET's gate power (PGATE) in calculating the power dissipation required for the FAN6520A:
PGATE = QG x VCC x FSW (17)
where QG is the total gate charge to reach VCC.
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FAN6520A
PRODUCT SPECIFICATION
Low-Side Losses
Q2, however, switches on or off with its parallel shottky diode conducting, therefore VDS 0.5V. Since PSW is proportional to VDS, Q2's switching losses are negligible and we can select Q2 based on RDS(ON) only. Conduction losses for Q2 are given by:
PCOND = (1-D) x IOUT2 x RDS(ON) (18)
The maximum power dissipation (PD(MAX) ) is a function of the maximum allowable die temperature of the low-side MOSFET, the J-A, and the maximum allowable ambient temperature rise:
T J ( MAX ) - T A ( MAX ) P D ( MAX ) = -----------------------------------------------J - A (19)
where RDS(ON) is the RDS(ON) of the MOSFET at the highest operating junction temperature and
V OUT D = -------------- is the minimum duty cycle for the converter. V IN
J-A, depends primarily on the amount of PCB area that can be devoted to heat sinking (see Fairchild app note AN-1029 for SO-8 MOSFET thermal information).
Since DMIN < 20% for portable computers, (1-D) 1 produces a conservative result, further simplifying the calculation.
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PRODUCT SPECIFICATION
FAN6520A
Typical Application Circuit
+5V D1 1 VCC C4 BOOT C6 C13 C12
5 2 HDRV SW
Q1
C5a
C5b
R5
U1 FAN6520A
L OUT Q2 C9-10 R6
R1 C3 R3 C7 R4 R7
8
+VOUT C11
4 3 COMP/OCSET 7 6 SW1
R2 C1 C2
LDRV GND FB
Figure 12. 5V to 1.5V 15A DC-DC Converter
Evaluation Board Bill of Materials (1.5V, 15 Amps):
Ref Des C1 C2 C3 C4 C5A,C5B C6,C11 C7 C9-10,C12,C13 D1 L1 Q1,Q2 R1 R2 R3 R4 R5 R6 R7 PB1 U1 TP1,2,3,4 Description 100pF Capacitor, 603 0.01F Capacitor, 603 Not Populated 0.1F Capacitor, 603 1F Capacitor, 805 0.1F Capacitor, 603 Not Populated Capacitor, 603 1500F Capacitor, 6.3V Diode, 30mA, 30V 1.2H Inductor Mosfet 2.2k 1% Resistor, 603 30.1k 1% Resistor, 603 Not Populated 2.49k Resistor, 603 11.8k Resistor, 603 Not Populated Resistor, 603 0 Resistor, 603 Pushbutton, miniature Single Synchronous Buck PWM Test Points Manufacturer Any Any - Any Any Any Any United Chemi-con Fairchild InterTechnical Fairchild Any Any - Any Any Any Any Digikey Fairchild KeyStone - - - - - - - KZJ6.3VB152M10X12LL MMSD4148 SC5015-1R2M FDD6606 - - - - - - - P8007S-ND FAN6520A 1514-2 P/N Qty 1 1 0 1 3 2 0 4 1 1 2 1 1 0 1 1 0 1 1 1 4
REV. 1.0.2 8/26/04
13
FAN6520A
PRODUCT SPECIFICATION
Dimensional Outline Drawing
4.900.10 3.81 8 5 B A
6.75 6.00 3.900.10 4.75
1.00 PIN ONE INDICATOR (0.33) 1.27 1 4 0.51 0.35 0.25
M
1.27 3.81
0.50
CBA
LAND PATTERN RECOMMENDATION
1.75 MAX 1.45+0.05 -0.20 C 0.10 0.15+0.10 -0.05 0.50 X 45 0.25 (R0.10) (R0.10) 8 0 GAGE PLANE 0.36 C
SEE DETAIL A
0.25 0.19
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, DATED MAY 1990. B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) STANDARD LEAD FINISH: 200 MICROINCHES / 5.08 MICRONS MIN. LEAD/TIN (SOLDER) ON COPPER.
0.700.20 (1.04) SEATING PLANE
DETAIL A
SCALE: 2:1
14
REV. 1.0.2 8/26/04
PRODUCT SPECIFICATION
FAN6520A
Ordering Information
Part Number FAN6520AM FAN6520AMX FAN6520AIM FAN6520AIMX Temperature Range 0C to 70C 0C to 70C -40C to 85C -40C to 85C Package SOIC-8 SOIC-8 SOIC-8 SOIC-8 Packing Rails Tape and Reel Rails Tape and Reel
DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com
8/26/04 0.0m 001 Stock#DS505602 2004 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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